For example, a computer system, such as a server or an information processing apparatus, in which a plurality of physical CPUs (Central Processing Units) share a memory space carries out an exchange of information between nodes through packet communication with each physical CPU acting as a node. A XB (Crossbar; Crossbar switch; Data transfer device) that is provided between the nodes and has a function of transferring data between the nodes requires a large-capacity RAM (Random Access Memory) as a buffer for data to be transferred.
FIG. 12 is a circuit diagram illustrating an example of the configuration of a buffer section in a data transfer circuit. The buffer section includes a write pointer register 11 that stores a write pointer; a read pointer register 12 that stores a read pointer; a storage section 13 that stores data; a write address selector 14 that selects a write address of the storage section 13 in accordance with the write pointer register 11; a read address selector 15 that selects a read address of the storage section 13 in accordance with the read pointer register 12; and a clock supply circuit 16 that supplies clocks to each portion of the storage section 13. In such a buffer section, writing and reading access to the storage section 13 is performed for each of the addresses per unit of time, and the address to be accessed is determined by the write pointer and the read pointer.
The write pointer register 11 and the read pointer register 12 are each realized by local counters. When an access demand emerges, the pointer registers each perform a writing or reading process of an address specified by the pointers (counter values) at the time and increase the pointers by one. That is, the pointer points to the next address to be accessed. When it is found that the pointers are equal to each other as a result of comparison of the pointers' values, then effectively the storage section 13 stores no data (“EMPTY” in FIG. 12). Accordingly, the reading of data from the storage section 13 is not performed. Therefore, it is possible to avoid underflow, which is caused by a reading access when the storage section 13 has no data.
FIG. 13 is a circuit diagram illustrating an example of a clock supply circuit that supplies clocks to the storage section. The clock supply circuit 16 includes a clock generation circuit 60 and continuously supplies clocks generated by the clock generation circuit 60 to all storage areas of the storage section 13. Incidentally, the clock generation circuit 60 may be provided outside the clock supply circuit 16 or the buffer section.
As a relevant technique, there is a data shift circuit designed to reduce power consumption.    [Patent Document 1] Japanese Laid-open Patent Publication No. 07-057492
The problem with the above clock supply circuit is that since clocks are continuously supplied to the storage section 13, power is consumed wastefully.